From: Julien Grall Date: Mon, 16 Feb 2015 14:50:42 +0000 (+0000) Subject: xen/arm: vgic-v3: Correctly set GICD_TYPER.CPUNumber X-Git-Tag: archive/raspbian/4.8.0-1+rpi1~1^2~3746 X-Git-Url: https://dgit.raspbian.org/%22http://www.example.com/cgi/%22/%22http:/www.example.com/cgi/%22?a=commitdiff_plain;h=834551bace5cfda7ca5ebbdc2ec9fd18f002e4ce;p=xen.git xen/arm: vgic-v3: Correctly set GICD_TYPER.CPUNumber On GICv3, the value (CPUNumber + 1) indicates the number of processor that may be used as interrupts targets when ARE bit is zero. The maximum is 8 processors. Signed-off-by: Julien Grall Acked-by: Ian Campbell --- diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index 72b22eea20..e0a7d5bd88 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -685,10 +685,15 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v, mmio_info_t *info) * Stream Protocol Interface */ unsigned int irq_bits = get_count_order(vgic_num_irqs(v->domain)); + /* + * Number of processors that may be used as interrupt targets when ARE + * bit is zero. The maximum is 8. + */ + unsigned int ncpus = min_t(unsigned int, v->domain->max_vcpus, 8); if ( dabt.size != DABT_WORD ) goto bad_width; /* No secure world support for guests. */ - *r = (((v->domain->max_vcpus << 5) & GICD_TYPE_CPUS ) | + *r = ((ncpus - 1) << GICD_TYPE_CPUS_SHIFT | ((v->domain->arch.vgic.nr_spis / 32) & GICD_TYPE_LINES)); *r |= (irq_bits - 1) << GICD_TYPE_ID_BITS_SHIFT; diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 187dc46e12..0396a8eed0 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -93,6 +93,7 @@ #define GICD_CTL_ENABLE 0x1 #define GICD_TYPE_LINES 0x01f +#define GICD_TYPE_CPUS_SHIFT 5 #define GICD_TYPE_CPUS 0x0e0 #define GICD_TYPE_SEC 0x400